-- components.vhd
-- Inners components for debug access
-- Oleg Gavrilchenko
-- reffum@bk.ru

library ieee;
use ieee.std_logic_1164.all;
use work.common.all;

package components is
   component alu is
   port(
      i_a, i_b       : in std_logic_vector(C_BUS_WIDTH - 1 downto 0);
      i_carry        : in std_logic;
      i_function     : in alu_functions;
      
      o_out          : out std_logic_vector(C_BUS_WIDTH - 1 downto 0);
      o_flags        : out status_flags
      );
   end component alu;
   
end components;
